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ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 displayport ? quad equalizer check for samples: ds32ev400 1 features description the ds32ev400 programmable quad equalizer 23 ? equalizes up to 14 db loss at 3.2 gbps provides compensation for transmission medium ? 8 levels of programmable equalization losses and reduces the medium-induced deterministic ? settable through control pins or smbus jitter for four nrz data channels. the ds32ev400 is interface optimized for operation up to 3.2 gbps for both cables and fr4 traces. each equalizer channel has ? operates up to 3.2 gbps with 40 ? fr4 traces eight levels of input equalization that can be ? 0.12 ui residual deterministic jitter at 3.2 programmed by three control pins, or individually gbps with 40 ? fr4 traces through a serial management bus (smbus) interface. ? single 2.5v or 3.3v power supply the device equalizes up to 14 db of loss at 3.2 gbps. ? signal detect for individual channels the equalizer supports both ac and dc-coupled data paths for long run length data patterns such as ? standby mode for individual channels prbs-31, and balanced codes such as 8b/10b. the ? supports ac or dc-coupling with wide input device uses differential current-mode logic (cml) common-mode inputs and outputs. ? low power consumption: 375 mw typ at 2.5v each channel has an independent signal detect ? small 7 mm x 7 mm 48-pin wqfn package output and independent enable input. the sd output ? 9 kv hbm esd rating maybe tied to the en to automatically control the power up and down of the channel. ? -40 to 85 c operating temperature range the ds32ev400 can be used in a variety of applications applications that include displayport, xaui, infiniband and other high-speed data transmission ? displayport applications. ? xaui the ds32ev400 is available in a 7 mm x 7 mm 48- ? infiniband pin leadless wqfn package. power is supplied from ? other 8b10b applications either a 2.5v or 3.3v supply. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 displayport is a trademark of video electronics standards association (vesa).. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2007 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com simplified application diagram 2 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400 asic/fpga high speed i/o backplane/cable sub-system switch fabric card line card out in ds32ev400 out in tx tx rx rx asic/fpga high speed i/o ds32ev400 4 4 4 4
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 pin descriptions pin name pin # i/o, type (1) description high speed differential i/o in_0+ 1 i, cml inverting and non-inverting cml differential inputs to the equalizer. an on-chip 100 ? in_0 ? 2 terminating resistor is connected between in_0+ and in_0-. refer to figure 6 . in_1+ 4 i, cml inverting and non-inverting cml differential inputs to the equalizer. an on-chip 100 ? in_1 ? 5 terminating resistor is connected between in_1+ and in_1-. refer to figure 6 . in_2+ 8 i, cml inverting and non-inverting cml differential inputs to the equalizer. an on-chip 100 ? in_2 ? 9 terminating resistor is connected between in_2+ and in_2-. refer to figure 6 . in_3+ 11 i, cml inverting and non-inverting cml differential inputs to the equalizer. an on-chip 100 ? in_3 ? 12 terminating resistor is connected between in_3+ and in_3-. refer to figure 6 . out_0+ 36 o, cml inverting and non-inverting cml differential outputs from the equalizer. an on-chip 50 ? out_0 ? 35 terminating resistor connects out_0+ to v dd and out_0- to v dd . out_1+ 33 o, cml inverting and non-inverting cml differential outputs from the equalizer. an on-chip 50 ? out_1 ? 32 terminating resistor connects out_1+ to v dd and out_1- to v dd . out_2+ 29 o, cml inverting and non-inverting cml differential outputs from the equalizer. an on-chip 50 ? out_2 ? 28 terminating resistor connects out_2+ to v dd and out_2- to v dd . out_3+ 26 o, cml inverting and non-inverting cml differential outputs from the equalizer. an on-chip 50 ? out_3 ? 25 terminating resistor connects out_3+ to v dd and out_3- to v dd . equalization control bst_2 37 i, lvcmos bst_2, bst_1, and bst_0 select the equalizer strength for all eq channels. bst_2 is bst_1 14 internally pulled high. bst_1 and bst_0 are internally pulled low. bst_0 23 device control en0 44 i, lvcmos enable equalizer channel 0 input. when held high, normal operation is selected. when held low, standby mode is selected. en is internally pulled high. en1 42 i, lvcmos enable equalizer channel 1 input. when held high, normal operation is selected. when held low, standby mode is selected. en is internally pulled high. en2 40 i, lvcmos enable equalizer channel 2 input. when held high, normal operation is selected. when held low, standby mode is selected. en is internally pulled high. en3 38 i, lvcmos enable equalizer channel 3 input. when held high, normal operation is selected. when held low, standby mode is selected. en is internally pulled high. feb 21 i, lvcmos force external boost. when held high, the equalizer boost setting is controlled by bst_[2:0] pins. when held low, the equalizer boost setting is controlled by smbus (see table 1 ) register bits. feb is internally pulled high. sd0 45 o, lvcmos equalizer ch0 signal detect output. produces a high when signal is detected. sd1 43 o, lvcmos equalizer ch1 signal detect output. produces a high when signal is detected. sd2 41 o, lvcmos equalizer ch2 signal detect output. produces a high when signal is detected. sd3 39 o, lvcmos equalizer ch3 signal detect output. produces a high when signal is detected. power v dd 3, 6, 7, power v dd = 2.5v 5% or 3.3v 10%. v dd pins should be tied to v dd plane through low inductance 10, 13, path. a 0.01 f bypass capacitor should be connected between each v dd pin to gnd planes. 15, 46 gnd 22, 24, power ground reference. gnd should be tied to a solid ground plane through a low impedance path. 27, 30, 31, 34 dap pad power ground reference. the exposed pad at the center of the package must be connected to ground plane of the board. serial management bus (smbus) interface control pins sda 18 i/o, lvcmos data input/output (bi-directional). internally pulled high. sdc 17 i, lvcmos clock input. internally pulled high. cs 16 i, lvcmos chip select. when pulled high, access to the equalizer smbus registers are enabled. when pulled low, access to the equalizer smbus registers are disabled. please refer to system management bus (smbus) and configuration registers for detailed information. other reserv 19, 20 reserved. do not connect. 47,48 (1) i = input, o = output copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: ds32ev400
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com connection diagram 4 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 in_3- in_3+ in_2- in_2+ in_1- in_1+ in_0- in_0+ out_3- out_3+ out_2- out_2+ out_1- out_1+ out_0- out_0+ v dd v dd v dd v dd gnd gnd gnd gnd v dd v dd gnd gnd bst_1 bst_0 cs sdc sda reserv v dd sd0 en0 sd1 en1 sd2 en2 sd3 en3 reserv bst_2 reserv reserv feb ds32ev400 top view dap = gnd
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) (2) supply voltage (v dd ) -0.5v to +4.0v cmos input voltage -0.5v + 4.0v cmos output voltage -0.5v to 4.0v cml input/output voltage -0.5v to 4.0v junction temperature +150 c storage temperature -65 c to +150 c lead temperature (soldering, 4 seconds) +260 c esd rating hbm, 1.5 k ? , 100 pf > 9 kv eiaj, 0 ? , 200pf > 250 v thermal resistance ? ja , no airflow 30 c/w (1) ? absolute maximum ratings ? indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. functional operation of the device and/or non-degradation at the absolute maximum ratings or other conditions beyond those indicated in the recommended operating conditions is not implied. the recommended operating conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. absolute maximum numbers are ensured for a junction temperature range of ? 40 c to +125 c. models are validated to maximum operating voltages only. (2) if military/aerospace specified devices are required, please contact the ti sales office/distributors for availability and specifications. recommended operating conditions min typ max units supply voltage (1) v dd2.5 to gnd 2.375 2.5 2.625 v v dd3.3 to gnd 3.0 3.3 3.6 v ambient temperature -40 25 +85 c (1) the v dd2.5 is v dd = 2.5v 5% and v dd3.3 is v dd = 3.3v 10%. copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: ds32ev400
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com electrical characteristics (1) over recommended operating supply and temperature ranges with default register settings unless other specified. symbol parameter conditions min typ (2) max units power p power supply consumption device output enabled 490 700 mw (en [0 ? 3] = high), v dd3.3 device output disable 100 mw (en [0 ? 3] = low), v dd3.3 p power supply consumption device output enabled 360 490 mw (en [0 ? 3] = high), v dd2.5 device output disable 30 (en [0 ? 3] = low), v dd2.5 n supply noise tolerance (3) 50 hz ? 100 hz 100 mv p-p 100 hz ? 10 mhz 40 mv p-p 10 mhz ? 1.6 ghz 10 mv p-p lvcmos dc specifications v ih high level input voltage v dd3.3 2.0 v dd3.3 v v dd2.5 1.6 v dd2.5 v v il low level input voltage -0.3 0.8 v v oh high level output voltage i oh = -3ma, v dd3.3 2.4 v i oh = -3ma, v dd2.5 2.0 v ol low level output voltage i ol = 3ma 0.4 v i in input leakage current v in = v dd +15 a v in = gnd -15 a i in-p input leakage current with internal v in = v dd , with internal pull-down +120 a pull-down/up resistors resistors v in = gnd, with internal pull-up -20 a resistors signal detect sdh signal detect on threshold level default input signal level to assert 70 mv p-p sd pin, 3.2 gbps sdi signal detect off threshold level default input signal level to de- 40 mv p-p assert sd, 3.2gbps cml receiver inputs (in_n+, in_n-) v tx source transmit launch signal ac-coupled or dc-coupled level (in diff) requirement, differential 400 1600 mv p-p measurement at point a. figure 1 v intre input threshold voltage differential measurement at 120 mv p-p point b. figure 1 v ddtx supply voltage of transmitter to dc-coupled requirement 1.6 v dd v eq ( (4) ) v icmdc input common mode voltage dc-coupled requirement, v ddtx ? v ddtx ? differential measurement at point v 0.8 0.2 a. figure 1 , ( (5) ) r li differential input return loss 100mhz ? 1.6ghz, with fixture ? s 10 db effect de-embedded r in input resistance differential across in+ and in-, 85 100 115 ? figure 6 . (1) the electrical characteristics tables list ensured specifications under the listed recommended operating conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. typical specifications are estimations only and are not ensured. (2) typical values represent most likely parametric norms at v dd = 3.3v, t a = 25 c, and at the recommended operation conditions at the time of product characterization and are not ensured. (3) allowed supply noise (mv p-p sine wave) under typical conditions. (4) recommended value. parameter not tested. (5) measured with clock like {11111 00000} pattern. 6 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 electrical characteristics (1) (continued) over recommended operating supply and temperature ranges with default register settings unless other specified. symbol parameter conditions min typ (2) max units cml outputs (out_n+, out_n-) v od output differential voltage level differential measurement with (out diff) out+ and out- terminated by 500 620 725 mv p-p 50 ? to gnd, ac-coupled figure 2 v ocm output common mode voltage single-ended measurement dc- v dd ? 0.2 v dd ? 0.1 coupled with 50 ? terminations v (6) t r , t f transition time 20% to 80% of differential output voltage, measured within 1 ? from 20 60 ps output pins. figure 2 , (6) r o output resistance single ended to v dd 42 50 58 ? r lo differential output return loss 100 mhz ? 1.6 ghz, with fixture ? s effect de-embedded. in+ = static 10 db high. t plhd differential low to high propagation delay measurement at 240 ps propagation delay 50% vo between input to output, 100 mbps. figure 3 , t phld differential high to low 240 ps (6) propagation delay t ccsk inter pair channel to channel difference in 50% crossing 7 ps skew between channels t ppsk part to part output skew difference in 50% crossing 20 ps between outputs equalization dj1 residual deterministic jitter 40 ? of 6 mil microstrip fr4, at 3.2 gbps eq setting 0x07, prbs-7 (2 7 -1) 0.12 0.20 ui p-p pattern. ( (7) (8) ) dj2 residual deterministic jitter 40 ? of 6 mil microstrip fr4, at 2.5 gbps eq setting 0x07, prbs-7 (2 7 -1) 0.1 0.16 ui p-p pattern. ( (7) (8) ) dj3 residual deterministic jitter 40 ? of 6 mil microstrip fr4, at 1 gbps eq setting 0x07, prbs-7 (2 7 -1) 0.05 ui p-p pattern. ( (7) (8) ) rj random jitter (6) (9) 0.5 psrms signal detect and enable timing t zisd input off to on detect ? sd response time measurement at 35 ns output high response time v in to sd output, v in = 800 mv p-p , 100 mbps, 40 ? of 6 mil microstrip t izsd input on to off detect ? sd fr4 400 ns output low response time see figure 1 and figure 4 (6) t ozoed en high to output on response response time measurement at 150 ns time en input to v o , v in = 800 mv p-p , 100 mbps, 40 ? of 6 mil microstrip t zoed en low to output off response fr4 5 ns time see figure 1 and figure 5 (6) (6) measured with clock like {11111 00000} pattern. (7) specification is ensured by characterization and is not tested in production. (8) deterministic jitter is measured at the differential outputs (point c of figure 1 ), minus the deterministic jitter before the test channel (point a of figure 1 ). random jitter is removed through the use of averaging or similar means. (9) random jitter contributed by the equalizer is defined as sqrt (j out 2 ? j in 2 ). j out is the random jitter at the equalizer outputs in ps-rms, see point c of figure 1 ; j in is the random jitter at the input of the equalizer in ps-rms, see figure 1 . copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: ds32ev400
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com electrical characteristics ? serial management bus interface over recommended operating supply and temperature ranges unless other specified. symbol parameter conditions min typ max units serial bus interface dc specifications v il data, clock input low voltage 0.8 v v ih data, clock input high voltage 2.1 v dd v i pullup current through pull-up resistor or high power specification 4 ma current source v dd nominal bus voltage 2.375 3.6 v i leak-bus input leakage per bus segment (1) -200 +200 a i leak-pin input leakage per device pin -15 a c i capacitance for sda and sdc (1) (2) 10 pf r term external termination resistance v dd3.3 2000 ? pull to v dd = 2.5v 5% or 3.3v (1) (2) (3) 10 v dd2.5 1000 ? (1) (2) (3) serial bus interface timing specifications ( figure 7 ) fsmb bus operating frequency (4) 10 100 khz tbuf bus free time between stop and 4.7 s start condition thd:sta hold time after (repeated) start at i pullup , max condition. after this period, the first 4.0 s clock is generated. tsu:sta repeated start condition setup 4.7 s time tsu:sto stop condition setup time 4.0 s thd:dat data hold time 300 ns tsu:dat data setup time 250 ns t timeout detect clock low timeout (4) 25 35 ms t low clock low period 4.7 s t high clock high period (4) 4.0 50 s t low :sext cumulative clock low extend time (4) 2 ms (slave device) t f clock/data fall time (4) 300 ns t r clock/data rise time (4) 1000 ns t por time in which a device must be (4) 500 ms operational after power-on reset (1) recommended value. parameter not tested. (2) recommended maximum capacitance load per bus segment is 400pf. (3) maximum termination voltage should be identical to the device supply voltage. (4) compliant to smbus 2.0 physical layer specification. see system management bus (smbus) specification version 2.0, section 3.1.1 smbus common ac specifications for details. 8 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 system management bus (smbus) and configuration registers the system management bus interface is compatible to smbus 2.0 physical layer specification. the use of the chip select signal is required . holding the cs pin high enables the smbus port allowing access to the configuration registers. holding the cs pin low disables the device's smbus allowing communication from the host to other slave devices on the bus. in the standby state, the system management bus remains active. when communication to other devices on the smbus is active, the cs signal for the ds32ev400s must be driven low. the address byte for all ds32ev400s is ac'h. based on the smbus 2.0 specification, the ds32ev400 has a 7- bit slave address of 1010110'b. the lsb is set to 0'b (for a write), thus the 8-bit value is 1010 1100'b or ac'h. the sdc and sda pins are 3.3v lvcmos signaling and include high-z internal pull up resistors. external low impedance pull up resistors maybe required depending upon smbus loading and speed. note, these pins are not 5v tolerant. transfer of data via the smbus during normal operation the data on sda must be stable during the time when sdc is high. there are three unique states for the smbus: start: a high-to-low transition on sda while sdc is high indicates a message start condition. stop: a low-to-high transition on sda while sdc is high indicates a message stop condition. idle: if sdc and sda are both high for a time exceeding t buf from the last detected stop condition or if they are high for a total exceeding the maximum specification for t high then the bus will transfer to the idle state. smbus transactions the device supports write and read transactions. see table 1 for register address, type (read/write, read only), default value and function information. writing a register to write a register, the following protocol is used (see smbus 2.0 specification). 1. the host (master) selects the device by driving its smbus chip select (cs) signal high. 2. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 3. the device (slave) drives the ack bit ( ? 0 ? ). 4. the host drives the 8-bit register address. 5. the device drives an ack bit ( ? 0 ? ). 6. the host drive the 8-bit data byte. 7. the device drives an ack bit ( ? 0 ? ). 8. the host drives a stop condition. 9. the host de-selects the device by driving its smbus cs signal low. the write transaction is completed, the bus goes idle and communication with other smbus devices may now occur. reading a register to read a register, the following protocol is used (see smbus 2.0 specification). 1. the host (master) selects the device by driving its smbus chip select (cs) signal high. 2. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 3. the device (slave) drives the ack bit ( ? 0 ? ). 4. the host drives the 8-bit register address. 5. the device drives an ack bit ( ? 0 ? ). 6. the host drives a start condition. 7. the host drives the 7-bit smbus address, and a ? 1 ? indicating a read. 8. the device drives an ack bit ? 0 ? . copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: ds32ev400
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com 9. the device drives the 8-bit data value (register contents). 10. the host drives a nack bit ? 1 ? indicating end of the read transfer. 11. the host drives a stop condition. 12. the host de-selects the device by driving its smbus cs signal low. the read transaction is completed, the bus goes idle and communication with other smbus devices may now occur. please see table 1 for more information. table 1. smbus register address name address default type ( bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1) status 0x00 0x00 ro id revision sd3 sd2 sd1 sd0 status 0x01 0x00 ro en1 boost 1 en0 boost 0 status 0x02 0x00 ro en3 boost 3 en2 boost 2 enable/ 0x03 0x44 rw en1 output boost control for ch1 en0 output boost control for ch0 boost (ch 0:enable 000 (min boost) 0:enable 000 (min boost) 0, 1) 1:disable 001 1:disable 001 010 010 011 011 100 (default) 100 (default) 101 101 110 110 111 (max boost) 111 (max boost) enable/ 0x04 0x44 rw en3 output boost control for ch3 en2 output boost control for ch2 boost (ch 0:enable 000 (min boost) 0:enable 000 (min boost) 2, 3) 1:disable 001 1:disable 001 010 010 011 011 100 (default) 100 (default) 101 101 110 110 111 (max boost) 111 (max boost) signal 0x05 0x00 rw sd3 on threshold sd2 on threshold sd1 on threshold sd0 on threshold detect select select select select 00: 70 mv (default) 00: 70 mv (default) 00: 70 mv (default) 00: 70 mv (default) 01: 55 mv 01: 55 mv 01: 55 mv 01: 55 mv 10: 90 mv 10: 90 mv 10: 90 mv 10: 90 mv 11: 75 mv 11: 75 mv 11: 75 mv 11: 75 mv signal 0x06 0x00 rw sd3 off threshold sd2 off threshold sd1 off threshold sd0 off threshold detect select select select select 00: 40 mv (default) 00: 40 mv (default) 00: 40 mv (default) 00: 40 mv (default) 01: 30 mv 01: 30 mv 01: 30 mv 01: 30 mv 10: 55 mv 10: 55 mv 10: 55 mv 10: 55 mv 11: 45 mv 11: 45 mv 11: 45 mv 11: 45 mv smbus 0x07 0x00 rw reserved smbus control enable control 0: disable 1: enable output 0x08 0x78 rw reserved output level: reserved level 00: 400 mv p-p 01: 540 mv p-p 10: 620 mv p-p (default) 11: 760 mv p-p (1) ro = read only, rw = read/write 10 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 figure 1. test setup diagram figure 2. cml output transition times figure 3. propagation delay timing diagram figure 4. signal detect (sd) delay timing diagram copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: ds32ev400 t izsd t zisd sd 0v 0v v dd 1.5v 1.5v in diff t plhd t phld out diff in diff 0v 0v ds32ev400 input output 6 mils trace width, fr4 microstrip test channel sma connector sma connector signal source a b c 0v 20% 80% 80% 20% out diff = (out+) (out-) t f t r
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com figure 5. enable (en) delay timing diagram figure 6. simplified receiver input termination circuit figure 7. smbus timing parameters 12 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400 sp t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta st sp t su:sto sdc sda cs t su:cs st 50 50 v dd 10k 6k in + eq in - 6k v dd 10k t ozed 0v v dd 1.5v en 1.5v 0v out diff t zoed
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 ds32ev400 functional descriptions the ds32ev400 is a programmable quad equalizer optimized for operation up to 3.2 gbps for backplane and cable applications. data channels the ds32ev400 provides four data channels. each data channel consists of an equalizer stage, a limiting amplifier, a dc offset correction block, and a cml driver as shown in figure 8 . figure 8. simplified block diagram equalizer boost control each data channel supports eight programmable levels of equalization boost. the state of the feb pin determines how the boost settings are controlled. if the feb pin is held high, then the equalizer boost setting is controlled by the boost set pins (bst_[2:0]) in accordance with table 2 . if this programming method is chosen, then the boost setting selected on the boost set pins is applied to all channels. when the feb pin is held low, the equalizer boost level is controlled through the smbus. this programming method is accessed via the appropriate smbus registers (see table 1 ). using this approach, equalizer boost settings can be programmed for each channel individually. feb is internally pulled high (default setting); therefore if left unconnected, the boost settings are controlled by the boost set pins (bst_[2:0]). the eight levels of boost settings enables the ds32ev400 to address a wide range of media loss and data rates. table 2. eq boost control table 6 mil microstrip fr4 24 awg twin-ax cable channel loss at 1.6 bst_n trace length (in) length (m) ghz (db) [2, 1, 0] 0 0 0 0 0 0 5 2 3 0 0 1 10 3 6 0 1 0 15 4 7 0 1 1 20 5 8 1 0 0 (default) 25 6 10 1 0 1 30 7 12 1 1 0 40 10 14 1 1 1 copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: ds32ev400 + - in_n + input termination equalizer limiting amplifier dc offset correction data channel (0-3) boost setting 3 3 3 bst_0:bst_2 bst cntl en en en - feb smbus register enn smbus register in_n out_n out_n sd sdn reg 07 bit 0 reg 03,04 bit 7, 3 v dd v dd
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com device state and enable control the ds32ev400 has an enable feature on each data channel which provides the ability to control device power consumption. this feature can be controlled either an enable pin (en_n) with reg 07 = 00'h (default value), or by the enable control bit register which can be configured through the smbus port (see table 1 and table 3 for detail register information), which require setting reg 07 = 01'h and changing register value of reg 03, 04. if the enable is activated using either the external en_n pin or smbus register, the corresponding data channel is placed in the active state and all device blocks function as described. the ds32ev400 can also be placed in standby mode to save power. in the standby mode only the control interface including the smbus port, as well as the signal detection circuit remain active. table 3. controlling device state reg. 07 bit 0 en pin (cmos) ch 0: device state reg. 03 bit 3 ch 1: reg. 03 bit 7 ch 2: reg. 04 bit 3 ch 3: reg. 04 bit 7 (en control) 0 : disable 1 x active 0 : disable 0 x standby 1 : enable x 0 active 1 : enable x 1 standby signal detect the ds32ev400 features a signal detect circuit on each data channel. the status of the signal of each channel can be determined by either reading the signal detect bit (sdn) in the smbus registers (see table 1 ) or by the state of each sdn pin. an output logic high indicates the presence of a signal that has exceeded the on threshold value (called sd_on). an output logic low means that the input signal has fallen below the off threshold value (called sd_off). these values are programmed via the smbus ( table 1 ). if not programmed via the smbus, the thresholds take on the default values as shown in table 4 . the signal detect threshold values can be changed through the smbus. all threshold values specified are dc peak-to-peak differential signals (positive signal minus negative signal) at the input of the device. table 4. signal detect threshold values channel 0: bit 1 channel 0: bit 0 sd_off threshold sd_on threshold channel 1: bit 3 channel 1: bit 2 register 06 (mv) register 05 (mv) channel2: bit 5 channel2: bit 4 channel 3: bit 7 channel 3: bit 6 0 0 40 (default) 70 (default) 0 1 30 55 1 0 55 90 1 1 45 75 output level control the output amplitude of the cml drivers for each channel can be controlled via the smbus (see table 1 ). the default output level is 620 mvp-p. table 5 presents the output level values supported: table 5. output level control settings all channels: bit 3 all channels: bit 2 output level register 08 (mv p-p ) 0 0 400 0 1 540 1 0 620 (default) 1 1 760 14 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 automatic enable feature it may be desirable to place unused channels in power-saving standby mode. this can be accomplished by connecting the signal detect (sdn) pin to the enable (enn) pin for each channel (see figure 9 ). in order for this option to function properly, the register value for reg. 07 should be 00'h (default value). if an input signal swing applied to a data channel is above the voltage level threshold as shown in table 4 , then the sdn output pin is asserted high. if the sdn pin is connected to the enn pin, this will enable the equalizer, limiting amplifier, and output buffer on the data channels; thus the ds32ev400 will automatically enter the active state. if the input signal swing falls below the sd_off threshold level, then the sdn output will be asserted low, causing the channel to be placed in the standby state. ds32ev400 applications information figure 9. automatic enable configuration displayport ? application the ds32ev400 maybe used to extend the reach of the cable for displayport applications. typical displayport cables are in the 6 meter range. with the ds32ev400 equalizer, nominal cables may be doubled to 12 meters in length. the quad devices supports 1, 2, or 4 channel applications. the ds32ev400 is compatible with the high speed video channels of displayport and can double the cable reach from six meters nominal to twelve meters. the ds32ev400 provides 20 db of equalization at 3 gbps and is well suited for the 2.7 gbps displayport application. lengths up to 10 meters of 28 awg can be supported on the input and 2 meters on the output for 12 meters total. the displayport aux channel is a low speed line and can be typically extended without the need of an equalizer. displayport also provides 1.5w of power in the cable which can be used to power the ds32ev400. a single channel version is also available (ds32ev100). unused equalizer channels it is recommended to put all unused channels into standby mode. general recommendations the ds32ev400 is a high performance circuit capable of delivering excellent performance. careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. refer to the lvds owner's manual for more detailed information on high speed design tips to address signal integrity design issues. pcb layout considerations for differential pairs the cml inputs and outputs must have a controlled differential impedance of 100 ? . it is preferable to route cml lines exclusively on one layer of the board, particularly for the input traces. the use of vias should be avoided if possible. if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. route the cml signals away from other signals and noise sources on the printed circuit board. see an-1187 ( snoa401 ) for additional information on wqfn packages. copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: ds32ev400 in_n r enn sdn equalizer limiting amplifier cml driver signal detect out_n r reg 07 = k? 00 (default)
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com power supply bypassing two approaches are recommended to ensure that the ds32ev400 is provided with an adequate power supply. first, the supply (v dd ) and ground (gnd) pins should be connected to power planes routed on adjacent layers of the printed circuit board. the layer thickness of the dielectric should be minimized so that the v dd and gnd planes create a low inductance supply with distributed capacitance. second, careful attention to supply bypassing through the proper use of bypass capacitors is required. a 0.01 f bypass capacitor should be connected to each v dd pin such that the capacitor is placed as close as possible to the ds32ev400. smaller body size capacitors can help facilitate proper component placement. additionally, three capacitors with capacitance in the range of 2.2 f to 10 f should be incorporated in the power supply bypassing design as well. these capacitors can be either tantalum or an ultra-low esr ceramic and should be placed as close as possible to the ds32ev400. dc coupling the ds32ev400 supports both ac coupling with external ac coupling capacitor, and dc coupling to its upstream driver, or downstream receiver. with dc coupling, users must ensure the input signal common mode is within the range of the electrical specification v icmdc and the device output is terminated with 50 to v dd . when power-up and power-down the device, both the ds32ev400 and the downstream receiver should be power-up and power- down together. this is to avoid the internal esd structures at the output of the ds32ev400 at power-down from being turned on by the downstream receiver. 16 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
ds32ev400 www.ti.com snls280f ? august 2007 ? revised april 2013 typical performance eye diagrams and curves figure 10. equalized signal figure 11. equalized signal (40 in fr4, 1 gbps, prbs7, 0x07 setting) (40 in fr4, 2.5gbps, prbs7, 0x07 setting) figure 12. equalized signal figure 13. equalized signal (40 in fr4, 3.2gbps, prbs7, 0x07 setting) (10m 24 awg twin-ax cable, 3.2 gbps, prbs7, 0x07 setting) figure 14. equalized signal figure 15. dj vs. eq setting (3.2 gbps) (32 in tyco xaui backplane, 3.125 gbps, prbs7, 0x07 setting) copyright ? 2007 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: ds32ev400
ds32ev400 snls280f ? august 2007 ? revised april 2013 www.ti.com revision history changes from revision e (april 2013) to revision f page ? changed layout of national data sheet to ti format .......................................................................................................... 17 18 submit documentation feedback copyright ? 2007 ? 2013, texas instruments incorporated product folder links: ds32ev400
package option addendum www.ti.com 8-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ds32ev400sq/nopb active wqfn nju 48 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 ds32ev400 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 8-oct-2015 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ds32ev400sq/nopb wqfn nju 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 q1 package materials information www.ti.com 2-sep-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ds32ev400sq/nopb wqfn nju 48 250 213.0 191.0 55.0 package materials information www.ti.com 2-sep-2015 pack materials-page 2
mechanical da t a nju0048d www .ti.com s q a 4 8 d ( r e v a )
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